CONTROL BYTE

TSC2008

The control byte (on SDI), as shown in Table 2, provides the start conversion, addressing, A/D converter

resolution, configuration, and power-down of the TSC2008. Figure 30, Table 2, and Table 3 give detailed

information regarding the order and description of these control bits within the control byte.

Table 2. Order of the Control Bits in the Control Byte

BIT 7

BIT 0

(MSB)

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

(LSB)

COMMENT

S

A2

A1

A0

MODE

SER/DFR

PD1

PD0

Excludes setup command

S

0

1

0

Pull-up

Bypass

Timing

Reset

Setup command

Table 3. Description of the Control Bits in the Control Byte

BIT

DESCRIPTION

Start Bit. When this bit = '1', it indicates this is one of the user commands. A new control byte can start every 16th clock cycle in

7

12-bit conversion mode or every 12th clock cycle in 8-bit conversion mode (see Figure 30 through Figure 33).

Bit[6:4] = A[2:0]. Channel select command if A[2:0]

≠

'010'.

These channel select bits, along with the SER/DFR bit,

6-4

Bit[6:4] = A[2:0]. Setup command if A[2:0] = '010'.

control the setting of the multiplexer input, touch driver

switches, and reference inputs (see Table 4 and

Figure 30 through Figure 33).

Mode Select Bit. This bit controls the number of bits for

the next conversion.

3

0: 50k

Ω PENIRQ pull-up resistor (default).

0: 12 bits (low)

1: 90k

Ω PENIRQ pull-up resistor.

1: 8 bits (high).

Single-Ended/Differential Reference Select Bit

(SER/DFR). Along with the channel select bits, A[2:0],

2

0: MAV noise filter enabled (default).

this bit controls the setting of the multiplexer input, touch

1: MAV noise filter bypassed.

driver switches, and reference inputs (see Table 4).

0: TSC2046-compatible timing for SDO during data read (default)

1: Adjusted SDO timing; MSB appears before 1st rising clock edge.

Bit[1:0] = PD[1:0]. Power Down Mode Select Bits.

1-0

See Table 5 for details.

Bit 0: Software Reset Bit.

0: Nothing happens (default).

1: Software reset.

(1)

These bits configure the pull-up resistor value, control the filter bypass, and select the SDO output timing. The bits are static and the

values are stored in register bits that will only be reset to default by a reset condition (power-on reset, software reset, or SureSet) or

changed with the setup command.

20

Submit Documentation Feedback

Copyright © 2008, Texas Instruments Incorporated

Product Folder Link(s): TSC2008