PIN CONFIGURATION

1

2

3

4

NC

NC

PENIRQ

SDO

X

-

Y+

X+

VDD/REF

13

14

15

16

8

7

6

5

TSC2008

ThermalPad

12

11

10

9

C lumns

o

(FRONTVIEW)

A

C

B

D

Y

-

GND

AUX

SCLK

X

-

X+

VDD/REF

3

2

1

PENIRQ

SDO

CS

Y+

SDI

TSC2008

RGV PACKAGE(1)(2)

YZG PACKAGE

4 x 4 QFN-16

WCSP-12

(TOP VIEW)

(TOP VIEW, SOLDER BUMPS ON BOTTOM SIDE)

(1)

The thermal pad is internally connected to

the substrate. The thermal pad can be

connected to the analog ground or left

floating. Keep the thermal pad separate

from the digital ground, if possible.

(2)

RGV (QFN) package available Q1, 2009.

PIN ASSIGNMENTS

PIN NO.

PIN

QFN

WCSP

NAME

I/O

A/D

DESCRIPTION

1

—

NC

No connection

2

B1

SDI

I

D

Serial data input

3

A1

CS

I

D

Chip select

4

A2

SCLK

I

D

Serial clock input

5

A3

VDD/REF

Supply voltage and external reference input

6

B3

X+

I

A

X+ channel input

7

C3

Y+

I

A

Y+ channel input

8

D3

X–

I

A

X– channel input

9

D2

Y–

I

A

Y– channel input

10

B2

GND

Ground

11

—

NC

No connection

12

C2

AUX

I

A

Auxiliary channel input. If not used, this input should be grounded.

13

—

NC

No connection

14

—

NC

No connection

Pen touch interrupt output. Active low when pen is touched. The output remains low until conversion is

15

D1

PENIRQ

O

D

complete or pen touch is released. The rising edge signals the end of conversion (EOC).

16

C1

SDO

O

D

Serial data output

Copyright © 2008, Texas Instruments Incorporated

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