7733 datasheet(231/940 Pages) RENESAS

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SERIAL I/O

7733 Group User’s Manual

8–28

Multiple transfer clock output pins can be selected

when performing only transmission with an internal

clock selected in UART0.

In this case, the CTS function cannot be used.

0 0: One transfer clock output pin

0 1:

1 0:

Multiple transfer clock output pins

1 1:

The CTS / RTS function selection bit is valid

when the CTS / RTS enable bit = “0.”

Note 2:

UART0 transmit/receive mode register (address 30 16)

UART1 transmit/receive mode register (address 38 16)

UART2 transmit/receive mode register (address 64 16)

Internal/External clock selection bit

0: Internal clock

1: External clock

: It may be “0” or “1.”

Clock synchronous serial I/O mode

Continued to

“Initial setting example for related registers when transmitting (2)”

on the next page

UART0 transmit/receive control register 0 (address 34 16)

UART1 transmit/receive control register 0 (address 3C 16)

BRG count source selection bits

CTS

/ RTS function selection bit (Note 2)

0: The CTS function is selected.

1: The RTS function is selected. (CTS function is disabled.)

CTS

/ RTS enable bit

0: The CTS / RTS function is enabled.

1: The CTS / RTS function is disabled.

Data output selection bit

0: TXDi pin is set for CMOS output.

1: TXDi pin is set for N-channel open-drain output.

CLK polarity selection bit

0: At the falling edge of the transfer clock, transmit data is output.

1: At the rising edge of the transfer clock, transmit data is output.

Transfer format selection bit

0: LSB first

1: MSB first

Clocks f 2, f 16, f 64, and f 512: Refer to chapter “14. CLOCK GENERATING CIRCUIT.”

0 0: Clock f2

0 1: Clock f16

1 0: Clock f64

1 1: Clock f512

b1 b0

Transmission clock output pin selection bits

Serial transmit control register (address 6E 16)

b5 b4

UART2 transmit/receive control register 0 (address 68 16)

BRG count source selection bits

CTS

enable bit

0: The CTS function is enabled.

1: The CTS function is disabled (I/O port).

0 0: Clock f2

0 1: Clock f16

1 0: Clock f64

1 1: Clock f512

b1 b0

Note 1: Nothing is implemented to bit 7 of UART2 transmit/receive mode register.

Fig. 8.3.3 Initial setting example for related registers when transmitting (1)

8.3 Clock synchronous serial I/O mode

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