7733 datasheet(232/940 Pages) RENESAS

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SERIAL I/O

7733 Group User’s Manual

8–29

UART0 transmission buffer register (address 32 16)

UART1 transmission buffer register (address 3A 16)

UART2 transmission buffer register (address 66 16)

Transmit data is set here.

Transmission is started.

UART0 baud rate register (BRG0) (address 31 16)

UART1 baud rate register (BRG1) (address 39 16)

UART2 baud rate register (BRG2) (address 65 16)

A value from 0016 to FF16 is set.

g Necessary only when internal clock is selected.

Port P8 register (address 12 16)

Set the output level of CLKS1 pin when not transferring

0: “L” (when clock polarity selection bit = “1”)

1: “H” (when clock polarity selection bit = “0”)

UART0 transmission interrupt control register (address 71 16)

UART1 transmission interrupt control register (address 73 16)

A-D/UART2 trans./rece. interrupt control register (address 70 16)

Interrupt priority level selection bits

When using interrupts, one of level 1 to 7 must be set.

When disabling interrupts, level 0 must be set.

Continued from

“Initial setting example for related registers when transmitting (1)”

on the preceding page

(If the CTS function is selected, transmission is started

when the CTSi pin’s input level is “L.”)

Port P8 direction register (address 14 16)

CLKS1 pin

CLKS0 pin

g1: Set this bit only when the number of the transfer clock

output pins is 3.

! : It may be “0” or “1.”

g2: Set this bit only when the number of the transfer clock

output pins is 2 or 3.

UART0 transmit/receive control register 1 (address 35 16)

UART1 transmit/receive control register 1 (address 3D 16)

UART2 transmit/receive control register 1 (address 69 16)

Transmit enable bit

1: Transmission is enabled.

Fig. 8.3.4 Initial setting example for related registers when transmitting (2)

8.3 Clock synchronous serial I/O mode

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