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SERIAL I/O

7733 Group User’s Manual

8–24

M37733MHBXXXFP

TXD0

CLKS1

CLKS0

CLK0

CLK

Note: This is applied when the following conditions are satisfied:

•Only transmission is performed.

•Clock synchronous serial I/O mode is selected.

•An internal clock is selected.

(4) Number of transfer clock output pins (UART0)

Only in UART0, when an internal clock is selected, one pin can be selected as the transfer clock

output pin from the following pins: CLK0, CLKS0 (in common with RxD0), and CLKS1 (in common with

____

CTS0

/RTS0).

By this selection, data can be transmitted to the maximum of three external receiving devices. (Refer

____

to in Table 8.3.4). In this case, since the RxD0 and CTS0/RTS0 pins function as the transfer clock

____ ____

output pins (CLK0, CLKS1), the CTS/RTS function and reception are disabled.

_____ ____

When only the CLK0 and CLKS0 pins are used as the transfer clock output pins, the P80 (CTS0/RTS0/

CLKS1) pin can be used as a programmable I/O port. (Refer to in Table 8.3.4.)

Also, when the CLK0 and CLKS1 pins are used as the transfer clock output pins and bit 2 of the port

P8 direction register is set to “0,” data can be received from the RxD0 pin. (Refer to in Table 8.3.4.)

[Setting for related registers]

q An internal clock is selected (bit 3 at address 3016 = “0”).

____ ____

q The CTS/RTS function is disabled (bit 4 at address 3416 = “1”).

q Reception is disabled (bit 2 at address 3516 = “0”). (Refer to and in Table 8.3.4.)

q Number of transfer clock output pins is selected. (bits 5 and 4 at address 6E16; Refer to Table

8.3.3.)

q Conditions for “output when not transferring” (described later) are set.

(CLKS0: bit 2 at address 1416 = “1”:

CLKS1: bit 0 at address 1416 = “1,” bit 0 at address 1216 = level at “output when not transferring”)

[Pin status]

Refer to Table 8.3.3.

Table 8.3.3 Pin functions when one transfer clock output pin is selected

Transfer clock

output pin

selection bits

Number of pins

from which one

transfer clock

output pin is

selected

Selectable

TxD0

(P83)

Outputs

serial data.

CLK0

(P81)

Outputs transfer clock.

Output when not transferring*

RxD0/CLKS0

(P82)

Programmable I/O port

Outputs transfer clock.

Output when not transferring*: When the CLK polarity selection bit (bit 6 at address 3416) = “0,” the CLK0

pin outputs “H” level; when this bit = “1,” the CLK0 pin outputs “L” level.

g When bit 2 at address 1416 (port P8 direction register) = “0,” the RxD0/CLKS0 pin is in a floating state;

when this bit = “1,” the RxD0/CLKS0 pin do the processing of “output when not transferring.”

Functions

Fig. 8.3.2 Connection example when one transfer clock output pin is selected from three pins

____

CTS0

/RTS0/CLKS1

(P80)

Programmable I/O port

Outputs transfer clock.

8.3 Clock synchronous serial I/O mode

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