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7733 датащи(PDF) 216 Page - Renesas Technology Corp |
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7733 датащи(HTML) 216 Page - Renesas Technology Corp |
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216 / 940 page ![]() SERIAL I/O 7733 Group User’s Manual 8–13 8.2.5 UARTi transmission register and UARTi transmission buffer register Figure 8.2.8 shows the block diagram for the transmitter. Figure 8.2.9 shows the structure of the UARTi transmission buffer register. Fig. 8.2.8 Block diagram for transmitter 8.2 Block description Fig. 8.2.9 Structure of UARTi transmission buffer register SP SP PAR “0” 2SP 1SP UART 7-bit UART 8-bit UART 7-bit UART 9-bit UART Clock sync. Clock sync. Clock sync. Data bus (even) Data bus (odd) TxDi UARTi transmission register Parity enabled Parity disabled D8 D7 D6 D5 D4 D3 D2 D1 D0 SP : Stop bit PAR : Parity bit UARTi transmission buffer register Bit converter 8-bit UART 9-bit UART (Note) Note: The bit converter is not assigned for UART2. b7 b0 (b15) (b8) b7 b0 UART0 transmission buffer register (addresses 33 16, 3216) UART1 transmission buffer register (addresses 3B 16, 3A16) UART2 transmission buffer register (addresses 67 16, 6616) Bit Not implemented. The transmit data is set. At reset Un- defined RW Functions 8 to 0 15 to 9 Un- defined WO — |
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