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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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7733 датащи(PDF) 215 Page - Renesas Technology Corp |
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7733 датащи(HTML) 215 Page - Renesas Technology Corp |
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215 / 940 page  SERIAL I/O 7733 Group User’s Manual 8–12 Bit Bit name At reset RW Functions b7 b6 b5 b4 b3 b2 b1 b0 Serial transmit control register (address 6E 16) g When using multiple transfer clock output pins, satisfy the following conditions: q Serial I/O mode selection bits (bits 2 to 0 at address 30 16) = “0012” q Internal/external clock selection bit (bit 3 at address 30 16) = “0” q CTS/RTS enable bit (bit 4 at address 34 16) = “1” q Receive enable bit (bit 2 at address 35 16) = “0” (for cases and in Table 8.3.4) q Transmission clock output pin selection bits = “01 2”, “102”, or “112” (Refer to Table 8.3.3.) Note: Bits 4 and 5 are ignored in the UART mode. (They may be “0” or “1.”) Not implemented. Un- defined 4 Transmission clock output pin selection bits (Valid only in the clock synchronous serial I/O mode.) (Note) 0 0 0: One transfer clock output pin (CLK0) 0 1: 1 0: 1 1: 5 0 0 3 to 0 7, 6 Not implemented. Value “0” is read out from here. b5 b4 Multiple transfer clock output pins — RW RW — 8.2.4 Serial transmit control register Figure 8.2.7 shows the structure of the serial transmit control register. The transmission clock output pin selection bits are valid only for UART0. For these bits, refer to section “8.3.1 Transfer clock.” 8.2 Block description Fig. 8.2.7 Structure of serial transmit control register |
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