7630 datasheet(29/238 Pages) RENESAS

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7630 Group User’s Manual

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I/O PORTS

The 7630 group has 35 programmable I/O pins and one input pin

arranged in five I/O ports (ports P0 to P4). The I/O ports are con-

trolled by the corresponding port registers and port direction regis-

ters; each I/O pin can be controlled separately.

When data is read from a port configured as an output port, the port

latch’s contents are read instead of the port level. A port configured

as an input port becomes floating and its level can be read. Data writ-

ten to this port will affect the port latch only; the port remains floating.

Refer to Structure of port- and port direction registers, Structure of

port I/Os (1) and Structure of port I/Os (2).

Fig. 10 Structure of port- and port direction registers

Fig. 11 Structure of port I/Os (1)

Port Pij direction control bit (j = 0 to 7)

0 : Port configured as input

1 : Port configured as output

Note : The direction control bits corresponding to P10, P11, P35, P36 and P37 are not

used (“0” when read, do not write “1”). Port direction registers are undefined when

read (write only).

Port Pi direction register (i = 0 to 4) (address 000916 + 2 · i)

PiD

Port Pij control bit (j = 0 to 7)

0 : “L” level

1 : “H” level

Note :

The control bits corresponding to P10, P35, P36 and P37 are not used

(“0” when read, do not write “1”).

Port Pi register (i = 0 to 4) (address 000816 + 2 · i)

(1) Ports P00/AN0 to P07/AN7

(2) Port P11/INT0

Data bus

Interrupt input

(3) Port P12/INT1

Data bus

Pull-up control bit

Port latch

Direction

Interrupt input

(4) Port P13/TX0

Data bus

Pull-up control bit

Port latch

direction

Timer bi-phase mode input

(5) Ports P14/CNTR0, P15/CNTR1

Data bus

Pull-up control bit

Port latch

Direction

Timer bi-phase mode input

(6) Port P16/PWM

Data bus

Pull-up control bit

Port latch

Direction

PWM output

PWM output enable

Data bus

Pull-up control bit

Port latch

Direction

ADC input

Analog input selection

I/O PORTS

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