7630 datasheet(13/238 Pages) RENESAS

13 / 238 page

List of figures

7630 GROUP USER’S MANUAL

vii

Fig. 2.5.20 Setting of related registers on transmitting side [Communication using UART] ........ 2-81

Fig. 2.5.21 Setting of related registers on receiving side [Communication using UART] ......... 2-82

Fig. 2.5.22 Control procedure on transmitting side [Communication using UART] ...... 2-83

Fig. 2.5.23 Control procedure on receiving side [Communication using UART] ........... 2-84

Fig. 2.5.24 Connection diagram [Communication using UART] ...................................... 2-85

Fig. 2.5.25 Timing chart [Communication using UART] ................................................... 2-85

Fig. 2.5.26 Setting of related registers on transmitting side [Communication using UART] ........ 2-86

Fig. 2.5.27 Setting of related registers on receiving side [Communication using UART] ............ 2-87

Fig. 2.5.28 Control procedure on transmitting side [Communication using UART] ...... 2-88

Fig. 2.5.29 Control procedure on receiving side [Communication using UART] ........... 2-89

Fig. 2.6.1 Memory map of A-D conversion related registers ........................................... 2-90

Fig. 2.6.2 Structure of A-D conversion register ................................................................. 2-91

Fig. 2.6.3 Structure of A-D control register ........................................................................ 2-91

Fig. 2.6.4 Connection diagram [Measurement of analog signals] ................................... 2-92

Fig. 2.6.5 Setting of related registers [Measurement of analog signals] ....................... 2-92

Fig. 2.6.6 Control procedure [Measurement of analog signals] ...................................... 2-93

Fig. 2.7.1 Structure of Watchdog timer register ................................................................ 2-94

Fig. 2.7.2 Set-up procedure of watchdog timer ................................................................. 2-95

Fig. 2.8.1 Example of Power on reset circuit .................................................................... 2-96

Fig. 2.8.2 RAM back-up system ........................................................................................... 2-96

Fig. 2.9.1 Memory map of oscillation circuit related registers ........................................ 2-97

Fig. 2.9.2 Structure of CPU mode register ........................................................................ 2-98

Fig. 2.9.3 Structure of Watchdog timer register ................................................................ 2-98

Fig. 2.9.4 Switching procedure to Stop mode ................................................................... 2-99

Fig. 2.9.5 Switching procedure to Wait mode .................................................................... 2-99

Fig. 2.10.1 Configuration example of using M37630T-RFS ......................................... 2-100

Fig. 2.11.1 Pin configuration of 7630 group’s built-in PROM versions ........................ 2-102

Fig. 2.11.2 Programming and testing of One Time PROM version .............................. 2-104

CHAPTER 3. APPENDIX

Fig. 3.1.1 Circuit for measuring output switching characteristics ...................................... 3-6

Fig. 3.1.2 Timing diagram ....................................................................................................... 3-7

Fig. 3.2.1 Icc-Vcc standard characteristics (in high-speed mode) .................................... 3-8

Fig. 3.2.2 Icc-Vcc standard characteristics (in middle-speed mode) ................................ 3-8

Fig. 3.2.3 Power source current standard characteristics (in high-speed mode) ........... 3-9

Fig. 3.2.4 Power source current standard characteristics (in middle-speed mode) ....... 3-9

Fig. 3.2.5 Output current standard characteristics (P-channel) ....................................... 3-10

Fig. 3.2.6 Output current standard characteristics (N-channel) ....................................... 3-10

Fig. 3.2.7 Pull-up transistor standard characteristics IIL-VI .......................................................... 3-11

Fig. 3.2.8 Pull-down transistor standard characteristics IIL-VI .................................................... 3-11

Fig. 3.2.9 A-D conversion standard characteristics ........................................................... 3-12

Fig. 3.3.1 Stack memory contents after instruction execution ......................................... 3-15

Fig. 3.3.2 Interrupt routine .................................................................................................... 3-16

____________

Fig. 3.4.1 Wiring for the RESET input pin ......................................................................... 3-17

Fig. 3.4.2 Wiring for clock I/O pins ..................................................................................... 3-17

Fig. 3.4.3 Wiring for the VPP pin of the One Time PROM and the EPROM version ................ 3-18

Fig. 3.4.4 Bypass capacitor across the VSS line and the VCC line ................................ 3-18

Fig. 3.4.5 Analog signal line and a resistor and a capacitor .......................................... 3-18

Fig. 3.4.6 Wiring for a large current signal line ................................................................ 3-19

Fig. 3.4.7 Wiring to a signal line where potential levels change frequently ................. 3-19

Fig. 3.4.8 VSS pattern on the underside of an oscillator ................................................. 3-20

Fig. 3.4.9 Setup for I/O ports ............................................................................................... 3-20

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