H8S2245 datasheet(248/818 Pages) RENESAS

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Section 7 Data Transfer Controller

Rev.3.00 Mar. 26, 2007 Page 206 of 772

REJ09B0355-0300

7.4

Interrupts

An interrupt request is issued to the CPU when the DTC finishes the specified number of data

transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation,

the interrupt set as the activation source is generated. These interrupts to the CPU are subject to

CPU mask level and interrupt controller priority level control.

In the case of activation by software, a software activated data transfer end interrupt (SWDTE

ND) is generated.

When one data transfer ends, or the specified number of data transfers end, with the DISEL bit set

to 1, after the end of the data transfer the SWDTE bit remains set to 1 and an SWDTEND interrupt

is generated.

The interrupt handling routine should clear the SWDTE bit to 0.

When the DTC is activated by software, an SWDTEND interrupt is not generated during a data

transfer wait or during data transfer even if the SWDTE bit is set to 1.

7.5

Usage Notes

Module Stop: When the MSTP14 bit in MSTPCR is set to 1, the DTC clock stops, and the DTC

enters the module stop state. However, 1 cannot be written in the MSTP14 bit while the DTC is

operating. See section 18, Power-Down Modes, for details.

On-Chip RAM: The MRA, MRB, SAR, DAR, CRA, and CRB registers are all located in on-chip

RAM. When the DTC is used, the RAME bit in SYSCR must not be cleared to 0.

DTCE Bit Setting: For DTCE bit setting, use bit manipulation instructions such as BSET and

BCLR. If all interrupts are masked, multiple activation sources can be set at one time by writing

data after executing a dummy read on the relevant register.

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