H8S2245 datasheet(218/818 Pages) RENESAS

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Section 6 Bus Controller

Rev.3.00 Mar. 26, 2007 Page 176 of 772

REJ09B0355-0300

6.9.3

Bus Transfer Timing

Even if a bus request is received from a bus master with a higher priority than that of the bus

master that has acquired the bus and is currently operating, the bus is not necessarily transferred

immediately. There are specific times at which each bus master can relinquish the bus.

CPU

The CPU is the lowest-priority bus master, and if a bus request is received from the DTC, the bus

arbiter transfers the bus to the bus master that issued the request. The timing for transfer of the bus

is as follows:

• The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in

discrete operations, as in the case of a longword-size access, the bus is not transferred between

the operations.

• If the CPU is in sleep mode, it transfers the bus immediately.

DTC

The DTC sends the bus arbiter a request for the bus when an activation request is generated.

The DTC can release the bus after a vector read, a register information read (3 states), a single data

transfer, or a register information write (3 states). It does not release the bus during a register

information read (3 states), a single data transfer, or a register information write (3 states).

6.9.4

External Bus Release Usage Note

External bus release can be performed on completion of an external bus cycle. The

RD signal

remains low until the end of the external bus cycle. Therefore, when external bus release is

performed, the

RD signal may change from the low level to the high-impedance state.

6.10

Resets and the Bus Controller

In a power-on reset, the H8S/2245, including the bus controller, enters the reset state at that point,

and an executing bus cycle is discontinued.

In a manual reset, the bus controller's registers and internal state are maintained, and an executing

external bus cycle is completed. In this case,

WAIT input is ignored and write data is not

guaranteed.

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