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H8S2245 датащи(PDF) 214 Page - Renesas Technology Corp

номер детали H8S2245
подробное описание детали  Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
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производитель  RENESAS [Renesas Technology Corp]
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Section 6 Bus Controller
Rev.3.00 Mar. 26, 2007 Page 172 of 772
REJ09B0355-0300
6.7.2
Pin States in Idle Cycle
Table 6.5 shows pin states in an idle cycle.
Table 6.5
Pin States in Idle Cycle
Pins
Pin State
A
23 to A0
Contents of next bus cycle
D
15 to D0
High impedance
CSn
High
AS
High
RD
High
HWR
High
LWR
High
6.8
Bus Release
6.8.1
Overview
The H8S/2245 Group can release the external bus in response to a bus request from an external
device. In the external bus released state, the internal bus master continues to operate as long as
there is no external access.
If an internal bus master wants to make an external access in the external bus released state, it can
issue a bus request off-chip.
6.8.2
Operation
In external expansion mode, the bus can be released to an external device by setting the BRLE bit
in BCRL to 1. Driving the
BREQ pin low issues an external bus request to the H8S/2245 Group.
When the
BREQ pin is sampled, at the prescribed timing the BACK pin is driven low, and the
address bus, data bus, and bus control signals are placed in the high-impedance state, establishing
the external bus-released state.
In the external bus released state, an internal bus master can perform accesses using the internal
bus. When an internal bus master wants to make an external access, it temporarily defers
activation of the bus cycle, and waits for the bus request from the external bus master to be
dropped.



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