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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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H8S2245 датащи(PDF) 222 Page - Renesas Technology Corp |
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H8S2245 датащи(HTML) 222 Page - Renesas Technology Corp |
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222 / 818 page  Section 7 Data Transfer Controller Rev.3.00 Mar. 26, 2007 Page 180 of 772 REJ09B0355-0300 7.2 Register Descriptions 7.2.1 DTC Mode Register A (MRA) 7 SM1 6 SM0 5 DM1 4 DM0 3 MD1 0 Sz 2 MD0 1 DTS Bit Initial value : : — Unde- fined R/W : — Unde- fined — Unde- fined — Unde- fined — Unde- fined — Unde- fined — Unde- fined — Unde- fined MRA is an 8-bit register that controls the DTC operating mode. Bits 7 and 6—Source Address Mode 1 and 0 (SM1, SM0): These bits specify whether SAR is to be incremented, decremented, or left fixed after a data transfer. Bit 7 Bit 6 SM1 SM0 Description 0 — SAR is fixed 1 0 SAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) 1 SAR is decremented after a transfer (by –1 when Sz = 0; by –2 when Sz = 1) Bits 5 and 4—Destination Address Mode 1 and 0 (DM1, DM0): These bits specify whether DAR is to be incremented, decremented, or left fixed after a data transfer. Bit 5 Bit 4 DM1 DM0 Description 0 — DAR is fixed 1 0 DAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) 1 DAR is decremented after a transfer (by –1 when Sz = 0; by –2 when Sz = 1) |
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