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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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H8S2245 датащи(PDF) 212 Page - Renesas Technology Corp |
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H8S2245 датащи(HTML) 212 Page - Renesas Technology Corp |
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212 / 818 page  Section 6 Bus Controller Rev.3.00 Mar. 26, 2007 Page 170 of 772 REJ09B0355-0300 (2) Write after Read If an external write occurs after an external read while the ICIS0 bit in BCRH is set to 1, an idle cycle is inserted at the start of the write cycle. This is enabled in advanced mode and normal mode. Figure 6.21 shows an example of the operation in this case. In this example, bus cycle A is a read cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented. T1 Address bus φ RD Bus cycle A Data bus T2 T3 T1 T2 Bus cycle B Long output floating time Data collision T1 Address bus φ RD Bus cycle A Data bus T2 T3 TI T1 Bus cycle B T2 HWR HWR CS (area A) CS (area B) CS (area A) CS (area B) (a) Idle cycle not inserted (ICIS0 = 0) (b) Idle cycle inserted (Initial value ICIS0 = 1) Figure 6.21 Example of Idle Cycle Operation (2) |
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