H8S2245 datasheet(208/818 Pages) RENESAS

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Section 6 Bus Controller

Rev.3.00 Mar. 26, 2007 Page 166 of 772

REJ09B0355-0300

6.6

Burst ROM Interface

6.6.1

Overview

With the H8S/2245 Group, external space area 0 can be designated as burst ROM space, and burst

ROM interfacing can be performed. The burst ROM space interface enables 16-bit configuration

ROM with burst access capability to be accessed at high speed.

Area 0 can be designated as burst ROM space by means of the BRSTRM bit in BCRH.

Consecutive burst accesses of a maximum of 4 words or 8 words can be performed for CPU

instruction fetches only. One or two states can be selected for burst access.

6.6.2

Basic Timing

The number of states in the initial cycle (full access) of the burst ROM interface is in accordance

with the setting of the AST0 bit in ASTCR. Also, when the AST0 bit is set to 1, wait state

insertion is possible. One or two states can be selected for the burst cycle, according to the setting

of the BRSTS1 bit in BCRH. Wait states cannot be inserted. When area 0 is designated as burst

ROM space, it becomes 16-bit access space regardless of the setting of the ABW0 bit in ABWCR.

When the BRSTS0 bit in BCRH is cleared to 0, burst access of up to 4 words is performed; when

the BRSTS0 bit is set to 1, burst access of up to 8 words is performed.

The basic access timing for burst ROM space is shown in figures 6.19 (a) and (b). The timing

shown in figure 6.19 (a) is for the case where the AST0 and BRSTS1 bits are both set to 1, and

that in figure 6.19 (b) is for the case where both these bits are cleared to 0.

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