M32CSLASH8A datasheet(140/372 Pages) RENESAS

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M32C/8A Group

13. DMAC

Rev.1.00

Jul 15, 2007

Page 123 of 352

REJ09B0385-0100

Table 13.2

DMiSL Register (i = 0 to 3) Function

NOTES:

When the INT3 pin is used for data bus in microprocessor mode, a DMA3 interrupt request cannot be generated by an input signal to

the INT3 pin.

The falling edge or both edges of input signal to the INTi pin can be a DMA request source. It is not affected by the INT interrupts (bits

POL and LVS in the INTiIC register, the IFSR register) and vice versa.

To switch between the UARTj receive interrupt and ACK interrupt (j = 0 to 4), use the IICM bit in the UiSMR register and IICM2 bit on

the UiSMR2 register. To use the ACK interrupt, set the IICM bit to 1 (I2C mode) and the IICM2 bit to 0 (NACK/ACK interrupt).

Setting Value

DMA Request Source

DMA0

DMA1

DMA2

DMA3

0000

Software trigger

0000

1Falling edge of INT0

Falling edge of INT1

Falling edge of INT2

Falling edge of INT3(1)

(Note 2)

0001

0Both edges of INT0

Both edges of INT1

Both edges of INT2

Both edges of INT3(1)

(Note 2)

0001

Timer A0 interrupt request

0010

Timer A1 interrupt request

0010

Timer A2 interrupt request

0011

Timer A3 interrupt request

0011

Timer A4 interrupt request

0100

Timer B0 interrupt request

0100

Timer B1 interrupt request

0101

Timer B2 interrupt request

0101

Timer B3 interrupt request

0110

Timer B4 interrupt request

0110

Timer B5 interrupt request

0111

UART0 transmit interrupt request

0111

UART0 receive interrupt or ACK interrupt request(3)

1000

UART1 transmit interrupt request

1000

UART1 receive interrupt or ACK interrupt request(3)

1001

UART2 transmit interrupt request

1001

UART2 receive interrupt or ACK interrupt request(3)

1010

UART3 transmit interrupt request

1010

UART3 receive interrupt or ACK interrupt request(3)

1011

UART4 transmit interrupt request

1011

UART4 receive interrupt or ACK interrupt request(3)

1100

A/D0 interrupt request

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