M32CSLASH8A datasheet(126/372 Pages) RENESAS

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M32C/8A Group

11. Interrupts

Rev.1.00

Jul 15, 2007

Page 109 of 352

REJ09B0385-0100

11.6.7

Returning from Interrupt Routine

When the REIT instruction is executed at the end of an interrupt routine, the values of the FLG register and PC,

which have been saved to the stack before the interrupt sequence is performed, are automatically restored. And

then, the program that was running before an interrupt request was acknowledged, resumes its process. The

high-speed interrupt uses the FREIT instruction instead. Refer to 11.4 High-Speed Interrupt for details.

Before executing the REIT or FREIT instruction, use the POPM instruction or the like to restore registers saved

by program in the interrupt routine. By executing the REIT or FREIT instruction, register bank is switched

back to the bank used immediately before the interrupt sequence.

11.6.8

Interrupt Priority

If two or more interrupt requests are detected at the same sampling points (a timing to detect whether any

interrupt request is generated or not), the interrupt with the highest priority is acknowledged.

Set bits ILVL2 to ILVL0 in the Interrupt Control Register to select the given priority level for maskable

interrupts (peripheral function interrupts).

Priority levels of special interrupts, such as NMI and watchdog timer interrupt are fixed by hardware. Figure

11.9 shows the priority of hardware interrupts.

The interrupt priority does not affect software interrupts. Executing an instruction for a software interrupt

causes the MCU to execute an interrupt routine.

Figure 11.9

Interrupt Priority of Hardware Interrupts

11.6.9

Interrupt Priority Level Select Circuit

The interrupt priority level select circuit selects the highest priority interrupt when two or more interrupt

requests are generated at the same sampling point.

Figure 11.10 shows the interrupt priority level select circuit.

Reset

NMI

Watchdog timer

Oscillation stop detection

Vdet4 detection

Peripheral function

Address match

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