M32CSLASH8A datasheet(108/372 Pages) RENESAS

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M32C/8A Group

9. Clock Generation Circuits

Rev.1.00

Jul 15, 2007

Page 91 of 352

REJ09B0385-0100

Figure 9.15

Procedure to Enter Stop Mode

Set an interrupt priority level of each interrupt

RLVL register: bits RLVL2 to RLVL0 = 7

Set the interrupt priority level (ILVL2 to ILVL0) of

the interrupt used to exit stop mode

I flag = 0

(1) Initial setting

Set the interrupt priority level of the interrupts,

which is not used to exit stop mode, to 0

FLG register: set IPL

Bits RLVL2 to RLVL0 = the same level as IPL

I flag = 1

CM1 register: CM10 bit = 1

(2) Before entering stop mode

Stop mode

RLVL register: bits RLVL2 to RLVL0 = 7

(3) After exiting wait mode

PRCR register: PRC0 bit = 1

PRC1 bit = 1

CM2 register: CM20 bit = 0

When the oscillation stop detect function is used

CM1 register: CM17 bit = 0

CM2 register: CM21 bit = 0

CM0 register: CM07 bit = 0

Select the main clock as the CPU clock source

(※Set after a main clock oscillation stabilizes)

Start

End

Set the wait/stop mode

exit interrupt priority level to 7.

Interrupt disabled

Set the exit interrupt priority level (RLVL2 to RLVL0)*

Enable writing to registers associated with clocks

Disable oscillation stop detect function

Interrupt enabled

All clocks stop(1)

Set the exit priority level as soon as exiting wait mode

> IPL* = (RLVL2 to RLVL0)*

(ILVL2 to ILVL0)

Set the processor interrupt priority level (IPL)*

NOTE:

1. Insert the jmp.b instruction as follows after the instruction to set the CM10 bit to 1.

bset 0,

cm1

; all clocks stopped (stop mode)

jmp.b LABEL_001 ; jmp.b instruction executed (no instruction

LABEL_001:

; between jmp.b and LABEL.)

nop

; nop(1)

nop

; nop(2)

nop

; nop(3)

nop

; nop(4)

mov.b #0, prcr

; protection set

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