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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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HD6417618 датащи(PDF) 155 Page - Renesas Technology Corp |
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HD6417618 датащи(HTML) 155 Page - Renesas Technology Corp |
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155 / 646 page  Section 7 Bus State Controller (BSC) Rev. 6.00 Jun. 12, 2007 Page 123 of 610 REJ09B0131-0600 Bit Bit Name Initial Value R/W Description 6 WM 0 R/W External Wait Mask Specification Specify whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait is valid 1: External wait is ignored 5 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0. • CS4WCR Bit Bit Name Initial Value R/W Description 31 to 21 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 20 BAS 0 R/W Byte Access Selection for Byte-Selection SRAM Specifies the WEn (BEn) and RD/WR signal timing when the byte-selection SRAM interface is used. 0: Asserts the WEn (BEn) signal at the read/write timing (signal used as strobe) and asserts the RD/ WR signal during the write access cycle (signal used as status) 1: Asserts the WEn (BEn) signal during the read/write access cycle (signal used as status) and asserts the RD/ WR signal at the write timing (signal used as strobe) 19 0 R Reserved This bit is always read as 0. The write value should always be 0. |
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