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HD6417618 датащи(PDF) 67 Page - Renesas Technology Corp |
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HD6417618 датащи(HTML) 67 Page - Renesas Technology Corp |
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67 / 646 page ![]() Section 2 CPU Rev. 6.00 Jun. 12, 2007 Page 35 of 610 REJ09B0131-0600 2.5 Instruction Set 2.5.1 Instruction Set by Type Table 2.10 lists the instructions classified by type. Table 2.10 Instruction Types Type Kinds of Instruction Op Code Function Number of Instructions MOV Data transfer Immediate data transfer Peripheral module data transfer Structure data transfer MOVA Effective address transfer MOVT T bit transfer SWAP Upper/lower swap Data transfer instructions 5 XTRCT Extraction of middle of linked registers 39 ADD Binary addition ADDC Binary addition with carry ADDV Binary addition with overflow CMP/cond Comparison DIV1 Division DIV0S Signed division initialization DIV0U Unsigned division initialization DMULS Signed double-precision multiplication DMULU Unsigned double-precision multiplication DT Decrement and test EXTS Sign extension EXTU Zero extension MAC Multiply-and-accumulate, double- precision multiply-and-accumulate Arithmetic operation instructions 21 MUL Double-precision multiplication 33 |
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