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HD6417618 датащи(PDF) 159 Page - Renesas Technology Corp

номер детали HD6417618
подробное описание детали  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
PDF  646 Pages
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производитель  RENESAS [Renesas Technology Corp]
домашняя страница  http://www.renesas.com
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HD6417618 датащи(HTML) 159 Page - Renesas Technology Corp

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Section 7 Bus State Controller (BSC)
Rev. 6.00 Jun. 12, 2007 Page 127 of 610
REJ09B0131-0600
Bit
Bit Name
Initial
Value
R/W
Description
10
9
8
7
WR3
WR2
WR1
WR0
1
0
1
0
R/W
R/W
R/W
R/W
Number of Access Wait Cycles
Specify the number of wait cycles that are necessary for
read access.
0000: 0 cycle
0001: 1 cycle
0010: 2 cycles
0011: 3 cycles
0100: 4 cycles
0101: 5 cycles
0110: 6 cycles
0111: 8 cycles
1000: 10 cycles
1001: 12 cycles
1010: 14 cycles
1011: 18 cycles
1100: 24 cycles
1101: Reserved (setting prohibited)
1110: Reserved (setting prohibited)
1111: Reserved (setting prohibited)
6
WM
0
R/W
External Wait Mask Specification
Specify whether or not the external wait input is valid. The
specification by this bit is valid even when the number of
access wait cycle is 0.
0: External wait is valid
1: External wait is ignored
5 to 2
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
1
0
HW1
HW0
0
0
R/W
R/W
Number of Delay Cycles from
RD, WEn (BEn) negation to
Address,
CSn negation
Specify the number of delay cycles from
RD and WEn
(
BEn) negation to address and CSn negation.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles



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