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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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HD6417618 датащи(PDF) 152 Page - Renesas Technology Corp |
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HD6417618 датащи(HTML) 152 Page - Renesas Technology Corp |
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152 / 646 page  Section 7 Bus State Controller (BSC) Rev. 6.00 Jun. 12, 2007 Page 120 of 610 REJ09B0131-0600 7.4.3 CSn Space Wait Control Register (CSnWCR) (n = 0, 3, 4, 5B, 6B) CSnWCR specifies various wait cycles for memory accesses. The bit configuration of this register varies as shown below according to the memory type (TYPE3, TYPE2, TYPE1, or TYPE0) specified by the CSn space bus control register (CSnBCR). Specify CSnWCR before accessing the target area. Specify CSnBCR first, then specify CSnWCR. Normal Space, Byte-Selection SRAM: • CS0WCR Bit Bit Name Initial Value R/W Description 31 to 13 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 12 11 SW1 SW0 0 0 R/W R/W Number of Delay Cycles from Address, CSn Assertion to RD, WEn (BEn) Assertion Specify the number of delay cycles from address and CSn assertion to RD and WEn (BEn) assertion. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles |
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