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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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HD6417618 датащи(PDF) 79 Page - Renesas Technology Corp |
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HD6417618 датащи(HTML) 79 Page - Renesas Technology Corp |
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79 / 646 page  Section 2 CPU Rev. 6.00 Jun. 12, 2007 Page 47 of 610 REJ09B0131-0600 2.6 Processing States 2.6.1 State Transition The CPU has the four processing states: reset, exception handling, program execution, and power- down. Figure 2.4 shows the CPU state transition. Note that some products do not support the manual reset function and the MRES pin. Software standby mode RES = 0 in any state RES = 1 and MRES = 0 in any state Power-on reset state Manual reset state Reset state Request for internal power-on reset or internal manual reset by the WDT Exception handling state Request for exception handling End of exception handling Program execution state SLEEP instruction by clearing SSBY bit SLEEP instruction by setting SSBY bit Sleep mode Request for NMI or IRQ interrupt Power-down mode Figure 2.4 CPU State Transition |
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