SH7616 datasheet(32/935 Pages) RENESAS

32 / 935 page

Section 1 Overview

Rev. 2.00 Mar 09, 2006 page 6 of 906

REJ09B0292-0200

Item

Specifications

Bus state controller

(BSC)

• Address space divided into five areas (CS0 to CS4, max. linear 32 Mbytes

each)

 Memory types such as DRAM, synchronous DRAM, burst ROM, can

be specified for each area

 Two synchronous DRAM spaces (CS2, CS3); CS3 also supports

DRAM

 Bus width (8, 16, 32 bits) can be selected for each area

 Wait state insertion control for each area

 Control signal output for each area

 Endian can be set for CS2 and CS4

• Cache

 Cache area/cache-through area selection by access address

 Selection of write-through or write-back mode

• Refresh functions

 CAS-before-RAS refreshing (auto refreshing) or self-refreshing

 Refresh interval settable by means of refresh counter and clock select

setting

 Concentrated refreshing according to refresh count setting

(1, 2, 4, 6, 8)

 Refresh request output possible (REFOUT)

• Direct DRAM interface

 Multiplexed row address/column address output

 Fast page mode burst transfer and continuous access when reading

 EDO mode

 TP cycle generation to secure RAS precharge time

• Direct synchronous DRAM interface

 Multiplexed row address/column address output

 Bank-active mode (valid for CS3 only)

 Selection of burst read/single write mode or burst read/burst write

mode

• Bus arbitration (BRLS, BGR)

• Refresh counter can be used as interval timer

 Interrupt request generated on compare match (CMI interrupt request

signal)

SH7616 датащи(PDF) 32 Page - Renesas Technology Corp