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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SH7616 датащи(PDF) 28 Page - Renesas Technology Corp |
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SH7616 датащи(HTML) 28 Page - Renesas Technology Corp |
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28 / 935 page  Section 1 Overview Rev. 2.00 Mar 09, 2006 page 2 of 906 REJ09B0292-0200 Table 1.1 Features Item Specifications CPU • Original Renesas architecture • 32-bit internal architecture • General register machine Sixteen 32-bit general registers Six 32-bit control registers (including 3 added for DSP use) Ten 32-bit system registers • RISC (Reduced Instruction Set Computer) type instruction set Fixed 16-bit instruction length for improved code efficiency Load-store architecture (basic operations are executed between registers) Delayed branch instructions reduce pipeline disruption during branches C-oriented instruction set • Instruction execution time: One instruction per cycle (16.0 ns/instruction at 62.5 MHz operation) • Address space: Architecture supports 4 Gbytes • On-chip multiplier: Multiply operations (32 bits × 32 bits → 64 bits) and multiply-and-accumulate operations (32 bits × 32 bits + 64 bits → 64 bits) executed in two to four cycles • Five-stage pipeline |
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