R8C2K datasheet(230/471 Pages) RENESAS

230 / 471 page

R8C/2K Group, R8C/2L Group

16. Timers

Rev.1.10

Dec 21, 2007

Page 213 of 450

REJ09B0406-0110

Figure 16.61

Operating Example of PWM2 Mode (Duty 0% and Duty 100%)

• TRCGRC register setting value greater than TRCGRA

TRC register value

Set to 0 by a

program

0000h

IMFB bit in

TRCSR register

IMFC bit in

TRCSR register

TSTART bit in

TRCMR register

TRCIOB output

The above applies under the following conditions:

• The TOB bit in the TRCCR1 register is set to 0 (initial level is “L”, “H” output at compare match with the TRCGRC register, “L” output at compare

match with the TRCGRB register).

• Bits TCEG1 and TCEG0 in the TRCCR2 register are set to 00b (TRCTRG trigger input disabled).

p+1

IMFA bit in

TRCSR register

“L” initial

output

No compare match with

TRCGRB register, so

“H” output continues

“H” output at TRCGRC register

compare match

m+1

• TRCGRB register setting value greater than TRCGRA

TRC register value

0000h

IMFB bit in

TRCSR register

IMFC bit in

TRCSR register

TSTART bit in

TRCMR register

TRCIOB output

n+1

IMFA bit in

TRCSR register

“L” initial

output

“L” output at

TRCGRB register

compare match

with no change.

No compare match

with TRCGRC register,

so “L” output continues

m+1

m: TRCGRA register setting value

n: TRCGRB register setting value

p: TRCGRC register setting value

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