R8C2K datasheet(229/471 Pages) RENESAS

229 / 471 page

R8C/2K Group, R8C/2L Group

16. Timers

Rev.1.10

Dec 21, 2007

Page 212 of 450

REJ09B0406-0110

Figure 16.60

Operating Example of PWM2 Mode (TRCTRG Trigger Input Enabled)

Set to 0 by

a program

TRC register value

Count source

m+1

n+1

0000h

FFFFh

p+1

TRCIOB output

m: TRCGRA register setting value

n: TRCGRB register setting value

p: TRCGRC register setting value

TSTART bit in

TRCMR register

Count stops

because the

CSEL bit is

set to 1

“L” initial output

“H” output at

TRCGRC register

compare match

IMFA bit in

TRCSR register

Set to 0 by

a program

IMFB bit in

TRCSR register

CSEL bit in

TRCCR2 register

IMFC bit in

TRCSR register

Transfer

TRCGRB register

TRCGRD register

Next data

Transfer

Transfer from buffer register to general register

The above applies under the following conditions:

• The TOB bit in the TRCCR1 register is set to 0 (initial level is “L”, “H” output at compare match with the TRCGRC register, “L” output at compare match with the

TRCGRB register).

• Bits TCEG1 and TCEG0 in the TRCCR2 register are set to 11b (trigger at both rising and falling edges of TRCTRG input).

Set to 0000h

by a program

Previous value

held if the

TSTART bit is

set to 0

The TSTART

bit is set to 0

TRC register cleared

at TRCGRA register

compare match

Return to initial value if the

TSTART bit is set to 0

TRC register (counter)

cleared at TRCTRG pin

trigger input

TRCTRG input

Count starts

TSTART bit

is set to 1

n+1

p+1

“L” output at

TRCGRB register

compare match

Inactive level so

TRCTRG input is

enabled

Active level so TRCTRG

input is disabled

Set to 0 by

a program

Set to 0 by

a program

Transfer

Transfer from buffer register to general register

Set to 1 by

a program

Changed by a program

Count starts at

TRCTRG pin

trigger input

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