R8C2K datasheet(228/471 Pages) RENESAS

228 / 471 page

R8C/2K Group, R8C/2L Group

16. Timers

Rev.1.10

Dec 21, 2007

Page 211 of 450

REJ09B0406-0110

Figure 16.59

Operating Example of PWM2 Mode (TRCTRG Trigger Input Disabled)

Set to 0 by a program

TRC register value

Count source

m+1

n+1

0000h

FFFFh

p+1

TRCIOB output

m: TRCGRA register setting value

n: TRCGRB register setting value

p: TRCGRC register setting value

TSTART bit in

TRCMR register

Count stops

because the

CSEL bit is

set to 1

“L” initial output

“H” output at TRCGRC

“L” output at TRCGRB

IMFA bit in

TRCSR register

Set to 0 by a program

IMFB bit in

TRCSR register

CSEL bit in

TRCCR2 register

Set to 1 by

a program

IMFC bit in

TRCSR register

Transfer

TRCGRB register

TRCGRD register

nNext data

Transfer

Transfer from buffer register to general register

The above applies under the following conditions:

• The TOB bit in the TRCCR1 register is set to 0 (initial level is “L”, “H” output at compare match with the TRCGRC register, “L” output at compare

match with the TRCGRB register).

• Bits TCEG1 and TCEG0 in the TRCCR2 register are set to 00b (TRCTRG trigger input disabled).

Set to 0000h

by a program

Previous value held if the

TSTART bit is set to 0

TSTART bit

is set to 0

TRC register cleared

at TRCGRA register

compare match

p+1

“H” output at TRCGRC register

compare match

No change

Return to initial output

if the TSTART bit is

set to 0

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