R8C2K datasheet(232/471 Pages) RENESAS

232 / 471 page

R8C/2K Group, R8C/2L Group

16. Timers

Rev.1.10

Dec 21, 2007

Page 215 of 450

REJ09B0406-0110

16.3.9

Notes on Timer RC

16.3.9.1

TRC Register

• The following note applies when the CCLR bit in the TRCCR1 register is set to 1 (clear TRC register at

compare match with TRCGRA register).

When using a program to write a value to the TRC register while the TSTART bit in the TRCMR register is

set to 1 (count starts), ensure that the write does not overlap with the timing with which the TRC register is

set to 0000h.

If the timing of the write to the TRC register and the setting of the TRC register to 0000h coincide, the

write value will not be written to the TRC register and the TRC register will be set to 0000h.

• Reading from the TRC register immediately after writing to it can result in the value previous to the write

being read out. To prevent this, execute the JMP.B instruction between the read and the write instructions.

Program Example

MOV.W

#XXXXh, TRC

;Write

JMP.B

;JMP.B instruction

L1:

MOV.W

TRC,DATA

;Read

16.3.9.2

TRCSR Register

Reading from the TRCSR register immediately after writing to it can result in the value previous to the write

being read out. To prevent this, execute the JMP.B instruction between the read and the write instructions.

Program Example

MOV.B

#XXh, TRCSR

;Write

JMP.B

;JMP.B instruction

L1:

MOV.B

TRCSR,DATA

;Read

16.3.9.3

Count Source Switching

• Stop the count before switching the count source.

Switching procedure

(1) Set the TSTART bit in the TRCMR register to 0 (count stops).

(2) Change the settings of bits TCK2 to TCK0 in the TRCCR1 register.

• After switching the count source from fOCO40M to another clock, allow a minimum of two cycles of f1 to

elapse after changing the clock setting before stopping fOCO40M.

Switching procedure

(1) Set the TSTART bit in the TRCMR register to 0 (count stops).

(2) Change the settings of bits TCK2 to TCK0 in the TRCCR1 register.

(3) Wait for a minimum of two cycles of f1.

(4) Set the FRA00 bit in the FRA0 register to 0 (high-speed on-chip oscillator off).

16.3.9.4

Input Capture Function

• The pulse width of the input capture signal should be three cycles or more of the timer RC operation clock

(refer to Table 16.11 Timer RC Operation Clock).

• The value of the TRC register is transferred to the TRCGRj register one or two cycles of the timer RC

operation clock after the input capture signal is input to the TRCIOj (j = A, B, C, or D) pin (when the

digital filter function is not used).

16.3.9.5

TRCMR Register in PWM2 Mode

When the CSEL bit in the TRCCR2 register is set to 1 (count stops at compare match with the TRCGRA

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