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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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M32C83T датащи(PDF) 91 Page - Renesas Technology Corp |
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M32C83T датащи(HTML) 91 Page - Renesas Technology Corp |
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91 / 527 page  Page 68 8 8 4 f o 6 0 0 2 , 1 3 . n a J 1 3 . 1 . v e R 1 3 1 0 - 4 3 0 0 B 9 0 J E R 8. Clock Generation Circuit ) T 3 8 / C 2 3 M , 3 8 / C 2 3 M ( p u o r G 3 8 / C 2 3 M Figure 8.3 CM1 Register CM10 (b4 - b1) (b5) (b6) CM17 System Clock Control Register 1(1) Reserved Bit All Clock Stop Control Bit(2) Reserved Bit Reserved Bit CPU Clock Select Bit 2(4) Set to "0" Set to "0" Set to "1" 0 : Clock oscillates 1 : All clocks stop (stop mode)(3) 0 : Main clock 1 : PLL clock Symbol Address After Reset CM1 000716 0010 00002 Function Bit Name Bit Symbol RW RW RW RW RW RW NOTES: 1. Rewrite the CM1 register after the PRC0 bit in the PRCR register is set to "1" (write enable). 2. When the CM10 bit is set to "1", XOUT becomes "H" and the internal feedback resistance is disabled. XIN, XCIN and XCOUT are placed in high-impedance states. 3. When the CM10 bit is set to "1", the MCD register is set to "0816" (divide-by-8 mode). When the CM20 bit is set to "1" (oscillation stop detect function enabled) or the CM21 bit to "1" (on-chip oscillator selected), do not set the CM10 bit to "1". 4. CM17 bit is enabled only when the CM21 bit in the CM2 register is set to "0". Use the procedure shown in Figure 8.13 to set the CM17 bit to "1". b7 b6 b5 b4 b3 b2 b1 b0 00 00 0 1 |
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