M32C83T datasheet(76/527 Pages) RENESAS

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Page 53

7. Bus

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7.1.1 Selecting External Address Bus

The number of externally-output address bus, chip-select signals and chip-select-assigned address

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space (CS area) varies depending on each external space mode. The PM11 to PM10 bits in the PM1

When using the DRAMC, row addresses and column addresses are multiplexed to output in the DRAM

area.

7.1.2 Selecting External Data Bus

The DS register selects either external 8-bit or 16-bit data bus per external space. The data bus in the

external space 3, after reset, becomes 16 bits wide when an "L" signal is applied to the BYTE pin and 8

bits wide when an "H" signal is applied. Do not change the BYTE pin level while the microcomputer is

operating. The internal bus is always 16 bits wide.

7.1.3 Selecting Separate/Multiplexed Bus

The PM05 to PM04 bits in the PM0 register determine either a separate or multiplexed bus as bus format .

7.1.3.1 Separate Bus

The separate bus is a bus format which allows the microcomputer to input and output data and ad-

dress using separate buses. The DS register selects 8-bit or 16-bit data bus as the external data bus

per external space. If all DSi bits in the DS register (i=0 to 3) are set to "0" (8-bit data bus), port P0

becomes the data bus and port P1 becomes the programmable I/O port. If one of the DSi bits is set to

"1" (16-bit data bus), ports P0 and P1 become the data bus. When the microcomputer accesses a

space while the DSi bit set to "0", port P1 is indeterminate.

If the microcomputer accesses a space with the separate bus, the WCR register determines the num-

ber of software wait states inserted.

7.1.3.2 Multiplexed Bus

The multiplexed bus is a bus format which allows the microcomputer to input and output data and

address via bus by timesharing. D0 to D7 are multiplexed with A0 to A7 in space accessed by the 8-bit

data bus. D0 to D15 are multiplexed with A0 to A15 in space accessed by the 16-bit data bus. If the

microcomputer accesses a space with the multiplexed bus, the WCR register can be set to either two

wait states or three wait states. Two-wait-state access is automatically selected if the WCR register is

set to no wait state or one wait state. Refer to 7.2.4 Bus Timing for details.

The microcomputer starts operation using the separate bus after reset. Therefore, the multiplexed bus

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can be assigned to access the CS1 area, the CS2 area, or all CS areas. However, the multiplexed bus

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cannot be assigned to access all CS areas in microprocessor mode. When the PM05 and PM04 bits

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in the PM0 register are set to "112" (access all CS areas with the bus), only 16 low-order bits, from A0

to A15, of an address are output. See Table 7.2 for details.

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