M32C83T datasheet(85/527 Pages) RENESAS

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Page 62

7. Bus

)

(

7.2.5 ALE Signal

The ALE signal latches an address of the multiplexed bus. Latch an address on the falling edge of the

ALE signal. The PM15 to PM14 bits in the PM1 register determine the output pin for the ALE signal.

The ALE signal is output to an internal space and external space.

Figure 7.6 ALE Signal and Address/Data Bus

_______

7.2.6 RDY Signal

_______

The RDY signal facilitates access to external devices which need longer access time. When an "L" signal

________

is applied to the RDY pin on the falling edge of last BCLK of the bus cycle, wait states are inserted into the

________

bus cycle. When an "H" signal is applied to the RDY pin on the falling edge of the BCLK, the bus cycle

starts running again.

________

Table 7.6 lists microcomputer states when the RDY signal inserts wait states into the bus cycle. Figure

_____

________

7.7 shows an example of the RD signal extended by the RDY signal.

Table 7.6 Microcomputer States in a Wait State(1)

Item

State

Oscillation

_____

RD Signal, WR Signal, Address Bus, CSi (i=0 to 3),

________

Maintains the same state as when RDY signal

__________

Data Bus, ALE Signal, HLDA, Programmable I/O Ports

was received

Internal Peripheral Circuits

NOTES:

________

1. The RDY signal cannot be accepted immediately before software wait states are inserted.

(1) 8-Bit Data Bus

(2) 16-Bit Data Bus

ALE

Address

Data

Address

D0/A0 to D7/A7

A8 to A15

ALE

Address

Data

Address

D0/A0 to D15/A15

A16 to A19

NOTES:

1. D0/A0 to D7/A7 are placed in high-impedance state when read.

2. When the multiplexed bus is selected for all CS areas, the address bus becomes an I/O port.

Address

Address or CS

A16 to A19

(1)

(2)

A20/CS3

A21/CS2

A22/CS1

A23/CS0

A20/CS3

A21/CS2

A22/CS1

A23/CS0

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