4553 datasheet(32/145 Pages) RENESAS

32 / 145 page

Rev.3.02

Dec 22, 2006

page 32 of 142

REJ03B0024-0302

4553 Group

Table 10 Timer related registers

CNTR pin output invalid

CNTR pin output valid

PWM signal “H” interval expansion function invalid

PWM signal “H” interval expansion function valid

Stop (state retained)

Operating

XIN input

Prescaler output (ORCLK)/2 signal output

CNTR pin output control bit

PWM signal interrupt valid waveform/

return level selection bit

Timer 2 control bit

Timer 2 count soruce selection bit

Timer control register W2

at power down : 00002

at reset : 00002

Notes 1: “R” represents read enabled, and “W” represents write enabled.

2: This function is valid only when the timer 1 count start synchronous circuit is selected (I10=“1”).

3: Port C output is invalid when CNTR input is selected for the timer 1 count source.

W23

W22

W21

W20

W11

Timer 1 count auto-stop circuit not selected

Timer 1 count auto-stop circuit selected

Stop (state retained)

Operating

Count source

PWM signal (PWMOUT)

Prescaler output (ORCLK)

Timer 3 underflow signal (T3UDF)

CNTR input

Timer 1 count auto-stop circuit selection

bit (Note 2)

Timer 1 control bit

Timer 1 count source selection bits

(Note 3)

W10

Timer control register W1

R/W

TAW1/TW1A

at power down : state retained

at reset : 00002

W13

W12

W11

W10

W31

XCIN input

Prescaler output (ORCLK)

Stop (Initial state)

Operating

Count value

Underflow occurs every 8192 counts

Underflow occurs every 16384 counts

Underflow occurs every 32768 counts

Underflow occurs every 65536 counts

Timer 3 count auto-stop circuit selection

bit

Timer 3 control bit

Timer 3 count value selection bits

W30

Timer control register W3

at power down : state retained

at reset : 00002

W33

W32

W31

W30

R/W

TAW2/TW2A

R/W

TAW3/TW3A

Stop (state retained)

Operating

Prescaler control bit

Timer control register PA

TPAA

at power down : 02

at reset : 02

PA0

Stop (state retained)

Operating

Bit 4 (T34) of timer 3

System clock (STCK)

CNTR output auto-control circuit not selected

CNTR output auto-control circuit selected

Falling edge

Rising edge

Timer LC control bit

Timer LC count source selection bit

CNTR output auto-control circuit

selection bit

CNTR pin input count edge selection bit

Timer control register W4

at power down : state retained

at reset : 00002

W43

W42

W41

W40

R/W

TAW4/TW4A

4553 датащи(PDF) 32 Page - Renesas Technology Corp

4553 датащи(HTML) 32 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL