4553 datasheet(49/145 Pages) RENESAS

49 / 145 page

Rev.3.02

Dec 22, 2006

page 49 of 142

REJ03B0024-0302

4553 Group

Fig. 39 Structure of reset pin and its peripherals,, and power-on reset operation

Name

D0–D4

D5/INT

XCIN/D6, XCOUT/D7

P00/SEG21–P03/SEG24

P10/SEG25–P13/SEG28

P20/SEG17–P23/SEG20

SEG0/VLC3–SEG2/VLC1

SEG3–SEG16

COM0–COM3

C/CNTR

Notes 1: Output latch is set to “1.”

2: Output structure is N-channel open-drain.

3: Pull-up transistor is turned OFF.

Function

D0–D4

XCIN, XCOUT

P00–P03

P10–P13

P20–P23

SEG0–SEG2

SEG3–SEG16

COM0–COM3

State

High-impedance (Notes 1, 2)

Sub-clock input

High-impedance (Notes 1, 2, 3)

VLC3 (VDD) level

“L” (VSS) level

(1) Power-on reset

Reset can be automatically performed at power on (power-on re-

set) by the built-in power-on reset circuit. When the built-in

power-on reset circuit is used, set the time for the supply voltage to

rise from 0 V to the minimum voltage of recommended operating

conditions to 100

µs or less.

If the rising time exceeds 100

µs, connect a capacitor between the

RESET pin and VSS at the shortest distance, and input “L” level to

RESET pin until the value of supply voltage reaches the minimum

operating voltage.

Table 13 Port state at reset

RESET pin

SRST instruction

Voltage drop detection circuit

(only for H version)

(Note 1)

Pull-up transistor

(Note 1)

Power-on reset circuit

VDD (Note 3)

100

µs or less

(Note 2)

Internal reset signal

Power-on

Reset released

Internal reset signal

Reset

state

Notes 1:

This symbol represents a parasitic diode.

2: Applied potential to RESET pin must be VDD or less.

3: Keep the value of supply voltage to the minimum value

or more of the recommended operating conditions.

circuit output

wer-on reset

Watchdog reset signal

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