4553 datasheet(52/145 Pages) RENESAS

52 / 145 page

Rev.3.02

Dec 22, 2006

page 52 of 142

REJ03B0024-0302

4553 Group

Table 15 Functions and states retained at power down mode

Function

Program counter (PC), registers A, B,

carry flag (CY), stack pointer (SP) (Note 2)

Contents of RAM

Interrupt control registers V1, V2

Interrupt control register I1

Selected oscillation circuit

Clock control register MR, RG

Timer 1 to timer 2 functions

Timer 3 function

Timer LC function

Watchdog timer function

Timer control registers PA

Timer control registers W1 to W4

LCD display function

LCD control registers L1 to L3, C1, C2

Voltage drop detection circuit

Port level

Pull-up control registers PU0, PU1

Key-on wakeup control registers K0 to K2

Port output structure control registers

FR0 to FR2

External interrupt request flag

(EXF0)

Timer interrupt request flags (T1F, T2F)

Timer interrupt request flag (T3F)

Interrupt enable flag (INTE)

Watchdog timer flags (WDF1, WDF2)

Watchdog timer enable flag (WEF)

(Note 3)

✕ (Note 4)

(Note 5)

(Note 6)

(Note 7)

(Note 3)

✕ (Note 4)

Notes 1:“O” represents that the function can be retained, and “✕” repre-

sents that the function is initialized.

Registers and flags other than the above are undefined at RAM

back-up, and set an initial value after returning.

2: The stack pointer (SP) points the level of the stack register and is

initialized to “7” at RAM back-up.

3: The state of the timer is undefined.

4: Initialize the watchdog timer with the WRST instruction, and then

go into the power down state.

5: LCD is turned off.

6: When the SVDE instruction is executed, this function is valid at

power down.

7: In the RAM back-up mode, C/CNTR pin outputs “L” level.

However, when the CNTR input is selected (W11, W10=“11”), C/

CNTR pin is in an input enabled state (output = high-impedance).

Other ports retain their respective output levels.

Power down mode

(Note 3)

✕ (Note 4)

(Note 6)

(Note 7)

(Note 3)

✕ (Note 4)

POWER DOWN FUNCTION

The 4553 Group has 2-type power down functions.

System enters into each power down state by executing the follow-

ing instructions.

• Clock operating mode ...................... EPOF and POF instructions

• RAM back-up mode ....................... EPOF and POF2 instructions

When the EPOF instruction is not executed before the POF or

POF2 instruction is executed, these instructions are equivalent to

the NOP instruction.

(1) Clock operating mode

The following functions and states are retained.

• RAM

• Reset circuit

• XCIN–XCOUT oscillation

• LCD display

• Timer 3

(2) RAM back-up mode

The following functions and states are retained.

• RAM

• Reset circuit

(3) Warm start condition

The system returns from the power down state when;

• External wakeup signal is input

• Timer 3 underflow occurs

in the power down mode.

In either case, the CPU starts executing the software from address

0 in page 0. In this case, the P flag is “1.”

(4) Cold start condition

The CPU starts executing the software from address 0 in page 0

when;

• reset pulse is input to RESET pin,

• reset by watchdog timer is performed, or

• reset by the voltage drop detection circuit is performed.

In this case, the P flag is “0.”

(5) Identification of the start condition

Warm start or cold start can be identified by examining the state of

the power down flag (P) with the SNZP instruction. The warm start

condition from the clock operating mode can be identified by exam-

ining the state of T3F flag.

Clock

operating

RAM

back-up

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