4553 datasheet(69/145 Pages) RENESAS

69 / 145 page

Rev.3.02

Dec 22, 2006

page 69 of 142

REJ03B0024-0302

4553 Group

CNTR pin output invalid

CNTR pin output valid

PWM signal “H” interval expansion function invalid

PWM signal “H” interval expansion function valid

Stop (state retained)

Operating

XIN input

Prescaler output (ORCLK)/2 signal output

CNTR pin output control bit

PWM signal interrupt valid waveform/

return level selection bit

Timer 2 control bit

Timer 2 count soruce selection bit

Timer control register W2

at power down : 00002

at reset : 00002

Notes 1: “R” represents read enabled, and “W” represents write enabled.

2: The oscillation circuit selected for system clock cannot be stopped.

3: This function is valid only when the timer 1 count start synchronous circuit is selected (I10=“1”).

4: Port C output is invalid when CNTR input is selected for the timer 1 count source.

W23

W22

W21

W20

Stop (state retained)

Operating

Prescaler control bit

Timer control register PA

TPAA

at power down : 02

at reset : 02

PA0

W11

Timer 1 count auto-stop circuit not selected

Timer 1 count auto-stop circuit selected

Stop (state retained)

Operating

Count source

PWM signal (PWMOUT)

Prescaler output (ORCLK)

Timer 3 underflow signal (T3UDF)

CNTR input

Timer 1 count auto-stop circuit selection

bit (Note 3)

Timer 1 control bit

Timer 1 count source selection bits

(Note 4)

W10

Timer control register W1

R/W

TAW1/TW1A

at power down : state retained

at reset : 00002

W13

W12

W11

W10

W31

XCIN input

Prescaler output (ORCLK)

Stop (Initial state)

Operating

Count value

Underflow occurs every 8192 counts

Underflow occurs every 16384 counts

Underflow occurs every 32768 counts

Underflow occurs every 65536 counts

Timer 3 count auto-stop circuit selection

bit

Timer 3 control bit

Timer 3 count value selection bits

W30

Timer control register W3

at power down : state retained

at reset : 00002

W33

W32

W31

W30

R/W

TAW2/TW2A

R/W

TAW3/TW3A

Sub-clock (f(XCIN)) oscillation available, ports D6 and D7 not selected

Sub-clock (f(XCIN)) oscillation stop, ports D6 and D7 selected

Main clock (f(XIN)) oscillation available

Main clock (f(XIN)) oscillation stop

On-chip oscillator (f(RING)) oscillation available

On-chip oscillator (f(RING)) oscillation stop

Sub-clock (f(XCIN)) control bit (Note 2)

Main-clock (f(XIN)) control bit (Note 2)

On-chip oscillator (f(RING)) control bit

(Note 2)

Clock control register RG

TRGA

at power down : state retained

at reset : 0002

RG2

RG1

RG0

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