7480 datasheet(33/98 Pages) RENESAS

33 / 98 page

MITSUBISHI MICROCOMPUTERS

7480/7481 GROUP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

PRELIMINAR

Notice:

This

is not

a final

specification.

Some

parametric

limits

are

subject

to change.

Each of the transmit and receive registers has a buffer register

(the same address on memory). Since the shift register cannot be

written to or read from directly, transmit data is written to the trans-

mit buffer register and receive data is read from the receive buffer

transmitted and receive 2-byte receive data in succession.

(2) Asynchronous Serial I/O (UART) Mode

The UART mode can be selected by clearing the serial I/O mode

selection bit of the serial I/O control register to “0”.

Eight serial data transfer formats can be selected, and the transfer

formats to be used by a transmitter and a receiver must be identi-

cal.

Fig. 30 Block diagram of UART serial I/O

Fig. 31 Operation of UART serial I/O function

Receive buffer register

Clock control circuit

Serial I/O control register

Baud rate generator

Serial I/O status register

1/4

Transmit shift register shift completion flag (TSC)

Transmit interrupt request (TI)

Transmit buffer empty flag (TBE)

Receive buffer full flag (RBF)

Receive interrupt request (RI)

Frequency division ratio 1/(n+1)

P14

P15

P16

Receive shift register

Transmit shift register

Transmit buffer register

TXD

SCLK

RXD

XIN

Address 00E016

Address 00E216

Address 00E016

Address 00E116

Address 00E416

7-bit

1/16

UART control register

ST/SP/PA generation

Serial I/O synchronous clock

selection bit (SCS)

SP detection

8-bit

ST detection

Address 00E316

Receive enable bit (RE)

Transmit enable bit (TE)

Character length

selection bit (CHAS)

Character length

selection bit

(CHAS)

BRG count source

selection bit (CSS)

Data bus

Serial I/O enable bit (SIOE)

Serial I/O synchronous clock selection bit (SCS)

Transmit interrupt

source selection bit (TIC)

Transmit or receive clock

Transmit buffer register

write signal

Serial output TxD

Receive buffer register

read signal

Serial input RxD

TBE=0

TSC=0

TBE=0

TBE=1

RBF=0

RBF=1

TSC=1

1 start bit

7/8 data bit

1/0 parity bit

1/2 stop bit

VGenerated at 2nd bit in 2

stop bit mode

Notes 1 : Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit during reception).

2 : The transmit interrupt (TI) can be selected to be generated when either TBE=1 or TSC=1, depending on the setting of

the transmit interrupt source selection bit of the serial I/O control register.

3 : The receive interrupt (RI) is set when the RBF flag becomes “1”.

TBE=1

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