7480 datasheet(40/98 Pages) RENESAS

40 / 98 page

MITSUBISHI MICROCOMPUTERS

7480/7481 GROUP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

PRELIMINAR

Notice:

This

is not

a final

specification.

Some

parametric

limits

are

subject

to change.

Watchdog Timer

The watchdog timer gives a means for returning to a reset status

when the program fails to run on its normal loop due to a runaway.

The watchdog timer consists of a 7-bit watchdog timer L and an 8-

bit watchdog timer H.

q Initial Value of Watchdog Timer

By a reset or writing to the watchdog timer H, the watchdog timer

H is set to “FF16” and the watchdog timer L is set to “7F16”. Any in-

struction that permits generating a write signal can be used; for

example, STA, LDM, CLB, etc. Write data has no significance, so

the above values are set regardless of that data.

q Operation of Watchdog Timer

The watchdog timer stops at reset, and writing a value in the

watchdog timer H causes it to start to count down. When bit 7 of

the watchdog timer H becomes “0”, an internal reset occurs.

The reset status is released as soon as the release reset time is

up. After that, the 7480/7481 group runs the program from the re-

set vector address. It is programmed that the watchdog timer H

can be set before bit 7 of the watchdog timer H is cleared to “0”. If

the watchdog timer H is never written, the watchdog timer does

not function. When the STP instruction is executed, the clock

stops and the watchdog timer also stops. The count is restarted as

soon as the stop mode is released. (Note) On the other hand, the

watchdog timer does not stop after execution of the WIT instruc-

tion.

The timing from writing to the watchdog timer H to clearing bit 7 of

the watchdog timer H to “0” is shown below. (f(XIN)=8 MHz)

• When bit 3 of the CPU mode register is “0” ............. 16.384 ms

• When bit 3 of the CPU mode register is “1” ............ 32.768 ms

Note: Since the watchdog timer still counts for the stop release

waiting time (about 2048 cycles of XIN), bit 7 of the watch-

dog timer H should not be cleared to “0” in this period.

Fig. 40 Block diagram of watchdog timer

Watchdog timer L (7)

Watchdog timer H (8)

1/8

1/16

“0”

“1”

Watchdog timer L count

source selection bit

Write “7F16” to the

watchdog timer register

Write “FF16” to the

watchdog timer register

Data bus

Reset circuit

Internal reset

RESET

f(XIN)

bit7

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