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M306V2EEFS датащи(PDF) 192 Page - Renesas Technology Corp

номер детали M306V2EEFS
подробное описание детали  SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
PDF  271 Pages
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производитель  RENESAS [Renesas Technology Corp]
домашняя страница  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

M306V2EEFS датащи(HTML) 192 Page - Renesas Technology Corp

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Rev.1.40
Oct 06, 2004 page 192 of 269
M306V2ME-XXXFP, M306V2EEFP
Figure 2.16.18 Relation between field determination flag and display font
Both HSYNC signal and VSYNC signal are negative-polarity input
Field
Even
Odd
Field
determination
flag(Note)
Display dot line
selection bit
Display dot line
0 (T2 > T1)
1 (T3 < T2)
0
1
0
1
When using the field determination flag, set bit 7 of the peripheral mode register (address 027D16) according to the main clock frequency.
T2
T3
OSD ROM font configuration diagram
Dot line 0
Dot line 1
Odd
Dot line 0
Dot line 1
(n - 1) field
(Odd-numbered)
T1
0.5 to 0.1 [ms] at
f(BCLK) = 10 MHz
CC mode · CDOSD mode
1
3
5
7911
13
15
1
3
5
7
9
11
13
15
17
19
21
23
25
26
24
22
20
18
16
14
12
10
8
6
4
2
24
6810
12
14
16
1
3
5
7
9
11
13
15
17
19
20
18
16
14
12
10
8
6
4
2
13
5
7
9
11
13
15
2
4
6
8
10
12
14
16
OSDS mode
HSYNC
VSYNC and
VSYNC
control
signal
in microcom-
puter
Upper :
VSYNC signal
Lower :
VSYNC control
signal in
micro-
computer
(n) field
(Even-numbered)
(n + 1) field
(Odd-numbered)
When the display dot line selection bit is “0,”
the “
” font is displayed at even field, the
“
” font is displayed at odd field. Bit 7 of the
I/O polarity control register can be read as the
field determination flag : “1” is read at odd field,
“0” is read at even field.
Note : The field determination flag changes at a rising edge of the VSYNC control signal (negative-polarity input) in
the microcomputer.



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