M306V2EEFS datasheet(191/271 Pages) RENESAS

191 / 271 page

Rev.1.40

Oct 06, 2004 page 191 of 269

M306V2ME-XXXFP, M306V2EEFP

2.16.5 Field Determination Display

To display the block with vertical dot size of 1/2H, whether an even field or an odd field is determined

through differences in a synchronizing signal waveform of interlacing system. The dot line 0 or 1 (refer to

Figure 2.16.18) corresponding to the field is displayed alternately.

In the following, the field determination standard for the case where both the horizontal sync signal and

the vertical sync signal are negative-polarity inputs will be explained. A field determination is determined

by detecting the time from a falling edge of the horizontal sync signal until a falling edge of the VSYNC

control signal (refer to Figure 2.16.9) in the microcomputer and then comparing this time with the time of

the previous field. When the time is longer than the comparing time, it is regarded as even field. When the

time is shorter, it is regarded as odd field.

The field determination flag changes at a rising edge of VSYNC control signal in the microcomputer .

The contents of this field can be read out by the field determination flag (bit 7 of the I/O polarity control

Figure 2.16.18).

However, the field determination flag read out from the CPU is fixed to “0” at even field or “1” at odd field,

regardless of bit 6.

Figure 2.16.17 I/O polarity control register

I/O polarity control register

HSYNC input

polarity switch bit

0 : Positive polarity input

1 : Negative polarity input

0 : Positive polarity input

1 : Negative polarity input

R, G, B output

polarity switch bit

0 : Positive polarity output

1 : Negative polarity output

VSYNC input

polarity switch bit

R W

Note: Refer to Figure 2.16.19.

0 : “

” at even field

“

” at odd field

1 : “

” at even field

“

” at odd field

OUT1 output

polarity switch bit

0 : Positive polarity output

1 : Negative polarity output

OUT2 output

polarity switch bit

0 : Positive polarity output

1 : Negative polarity output

Display dot line

selection bit

(See note)

Field determination

flag

0 : Even field

1 : Odd field

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

Bit symbol

Bit name

Function

Address

020616

When reset

1000X0002

PC0

PC1

PC2

PC4

PC5

PC6

PC7

Must always be set to “0.”

Reserved bit

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