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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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M306V2EEFS датащи(PDF) 189 Page - Renesas Technology Corp |
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M306V2EEFS датащи(HTML) 189 Page - Renesas Technology Corp |
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189 / 271 page  Rev.1.40 Oct 06, 2004 page 189 of 269 M306V2ME-XXXFP, M306V2EEFP 2.16.3 Dot Size The dot size can be selected by a block unit. The dot size in vertical direction is determined by dividing HSYNC in the vertical dot size control circuit. The dot size in horizontal is determined by dividing the following clock in the horizontal dot size control circuit : the clock gained by dividing the OSD clock source (data slicer clock, OSC1, main clock) in the pre-divide circuit. The clock cycle divided in the pre-divide circuit is defined as 1TC. The dot size is specified by bits 3 to 6 of the block control register. Refer to Figure 2.16.4 (the block control register i), refer to Figure 2.16.15 (the clock control register). The block diagram of dot size control circuit is shown in Figure 2.16.13. Notes 1 : The pre-divide ratio = 3 cannot be used in the CC mode. 2 : The pre-divide ratio of the layer 2 must be same as that of the layer 1 by the block control register i. 3 : In the bi-scan mode, the dot size in the vertical direction is 2 times as compared with the normal mode. Refer to “2.16.18 Scan Mode” about the scan mode. Figure 2.16.13 Block diagram of dot size control circuit Figure 2.16.14 Definition of dot sizes HSYNC Synchronous circuit Cycle✕2 Cycle✕3 Pre-divide circuit Clock cycle = 1TC Horizontal dot size control circuit Vertical dot size control circuit OSD control circuit Data slicer clock (See note) OSC1 Note: To use data slicer clock, set bit 0 of data slicer control register 1 to “0.” 1 dot Scanning line of F1 (F2) Scanning line of F2 (F1) 1/2H 1H 2H 3H 3TC 2TC 1TC 1TC In normal scan mode |
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