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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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M306V2EEFS датащи(PDF) 135 Page - Renesas Technology Corp |
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M306V2EEFS датащи(HTML) 135 Page - Renesas Technology Corp |
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135 / 271 page  Rev.1.40 Oct 06, 2004 page 135 of 269 M306V2ME-XXXFP, M306V2EEFP (3) I2Ci address register (i = 0, 1) _______ The I2Ci address register consists of a 7-bit slave address and a read/write bit. In the addressing mode, the slave address written in this register is compared with the address data to be received immediately after the START condition are detected. _______ s Bit 0: read/write bit (RBW) Not used when comparing addresses, in the 7-bit addressing mode. In the 10-bit addressing mode, the first address data to be received is compared with the contents (SAD6 to SAD0 + RBW) of the I2Ci address register. The RBW bit is cleared to “0” automatically when the stop condition is detected. s Bits 1 to 7: slave address (SAD0–SAD6) These bits store slave addresses. Regardless of the 7-bit addressing mode and the 10-bit addressing mode, the address data transmitted from the master is compared with the contents of these bits. Fig. 2.11.37 I2Ci address register (i = 0, 1) I2Ci address register (i = 0, 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset IIC0S0D 02E116 0016 IIC1S0D 02E916 0016 RBW Read/write bit <Only in 10-bit addressing (in slave) mode> The last significant bit of address data is compared. 0 : Wait the first byte of slave address after START condition (read state) 1 : Wait the first byte of slave address after RESTART condition (write state) SAD0 SAD1 SAD2 SAD3 SAD4 SAD5 SAD6 Slave address <In both modes> The address data is compared. Bit Symbol Bit name Function R W |
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