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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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M306V2EEFS датащи(PDF) 132 Page - Renesas Technology Corp |
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M306V2EEFS датащи(HTML) 132 Page - Renesas Technology Corp |
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132 / 271 page  Rev.1.40 Oct 06, 2004 page 132 of 269 M306V2ME-XXXFP, M306V2EEFP Fig. 2.11.34 I2Ci port selection register (i = 0, 1) (1) I2Ci port selection register (i = 0, 1) The I2Ci port selection register consists of bit to validate the multi-master I2C-BUS interface i function. s Bit 2: Multi-master I2C-BUS interface valid bit (FIICON) When this bit is “0,” the multi-master I2C-BUS interface i is nonactive; when “1,” it is active. When selecting active, multi-master I2C-BUS interface 0 is connected with the ports selected by bits 0 and 1 of the peripheral mode register (address 027D16) and multi-master I2C-BUS interface 1 is connected with the ports P93 and P94. Note: It needs 10-BCLK cycles from setting this bit to “1” to being active of multi-master I2C-BUS interface i. Accordingly, do not access multi-master I2C-BUS interface i-related registers in this period. I2Ci port selection register (i = 0, 1) b7 0 b6 0 b5 0 b4 00 00 b3 b2 b1 b0 Symbol Address When reset IIC0S2D 02E516 00??00002 IIC1S2D 02ED16 00??00002 RW FIICON Multi-master I 2C-BUS interface valid bit 0 : Nonactive 1 : Active Must always be set to “0” Reserved bits Must always be set to “0” Reserved bits Bit Symbol Bit name Function |
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