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Electrical Characteristics

MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev. 0

Freescale Semiconductor

Table 11 summarizes the reset actions that occur as a result of the different reset sources.

2.5.4.1

Power-On Reset (PORESET) Pin

Asserting PORESET initiates the power-on reset flow. PORESET must be asserted externally for at least 16 CLKIN cycles after

VDD and VDDH are both at their nominal levels.

Table 10. Reset Sources

Name

Direction

Description

Power-on reset

(PORESET)

Input

Initiates the power-on reset flow that resets the MSC8112 and configures various attributes of the

MSC8112. On PORESET, the entire MSC8112 device is reset. SPLL states is reset, HRESET and

SRESET are driven, the SC140 extended cores are reset, and system configuration is sampled. The

clock mode (MODCK bits), reset configuration mode, boot mode, Chip ID, and use of either a DSI 64

bits port or a System Bus 64 bits port are configured only when PORESET is asserted.

External hard

reset (HRESET)

Input/ Output

Initiates the hard reset flow that configures various attributes of the MSC8112. While HRESET is

asserted, SRESET is also asserted. HRESET is an open-drain pin. Upon hard reset, HRESET and

SRESET are driven, the SC140 extended cores are reset, and system configuration is sampled. The

most configurable features are reconfigured. These features are defined in the 32-bit hard reset

configuration word described in Hard Reset Configuration Word section of the Reset chapter in the

MSC8112 Reference Manual.

External soft reset

(SRESET)

Input/ Output

Initiates the soft reset flow. The MSC8112 detects an external assertion of SRESET only if it occurs

while the MSC8112 is not asserting reset. SRESET is an open-drain pin. Upon soft reset, SRESET is

driven, the SC140 extended cores are reset, and system configuration is maintained.

Software

watchdog reset

Internal

When the MSC8112 watchdog count reaches zero, a software watchdog reset is signalled. The

enabled software watchdog event then generates an internal hard reset sequence.

Bus monitor reset

Internal

When the MSC8112 bus monitor count reaches zero, a bus monitor hard reset is asserted. The

enabled bus monitor event then generates an internal hard reset sequence.

Host reset

command through

the TAP

Internal

When a host reset command is written through the Test Access Port (TAP), the TAP logic asserts the

soft reset signal and an internal soft reset sequence is generated.

Table 11. Reset Actions for Each Reset Source

Reset Action/Reset Source

Power-On

Reset

(PORESET)

Hard Reset (HRESET)

Soft Reset (SRESET)

External only

External or Internal

(Software Watchdog or

Bus Monitor)

External

JTAG Command:

EXTEST, CLAMP, or

HIGHZ

Configuration pins sampled (Refer to

Section 2.5.4.1 for details).

Yes

NoNoNo

SPLL state reset

Yes

System reset configuration write through

the DSI

Yes

NoNoNo

System reset configuration write though

the system bus

Yes

HRESET driven

Yes

SIU registers reset

Yes

IPBus modules reset (TDM, UART,

Timers, DSI, IPBus master, GIC, HS, and

GPIO)

Yes

SRESET driven

Yes

Depends on command

SC140 extended cores reset

Yes

MQBS reset

Yes

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