MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev. 0

Electrical Characteristics

Freescale Semiconductor

18

2.5.3

Clock and Timing Signals

The following sections include a description of clock signal characteristics. Table 7 shows the maximum frequency values for

frequency values are not exceeded.

2.5.4

Reset Timing

The MSC8112 has several inputs to the reset logic:

•

•

•

•

Software watchdog reset

•

Bus monitor reset

•

Host reset command through JTAG

All MSC8112 reset sources are fed into the reset controller, which takes different actions depending on the source of the reset.

The reset status register indicates the most recent sources to cause a reset. Table 10 describes the reset sources.

Table 7. Maximum Frequencies

Characteristic

Maximum in MHz

Core frequency

300

Reference frequency (REFCLK)

100

Internal bus frequency (BLCK)

100

DSI clock frequency (HCLKIN)

HCLKIN

≤ (min{70 MHz, CLKOUT})

External clock frequency (CLKIN or CLKOUT)

100

Table 8. Clock Frequencies

Characteristics

Symbol

Min

Max

CLKIN frequency

20

100

BCLK frequency

40

100

Reference clock (REFCLK) frequency

40

100

Output clock (CLKOUT) frequency

40

100

SC140 core clock frequency

200

300

Note:

The rise and fall time of external clocks should be 3 ns maximum

Table 9. System Clock Parameters

Characteristic

Min

Max

Unit

Phase jitter between BCLK and CLKIN

—

0.3

ns

CLKIN frequency

20

see Table 8

MHz

CLKIN slope

—3

ns

—

150

ps

CLKIN jitter spectrum

150

—

KHz

PLL input clock (after predivider)

20

100

MHz

PLL output frequency (VCO output)

800

1200

MHz

—

200

ps

—

500

ps

Notes:

1.

Peak-to-peak.

2.

Not tested. Guaranteed by design.