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MSC8112 датащи(PDF) 30 Page - Freescale Semiconductor, Inc

номер детали MSC8112
подробное описание детали  Dual Core Digital Signal Processor
PDF  44 Pages
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производитель  FREESCALE [Freescale Semiconductor, Inc]
домашняя страница  http://www.freescale.com
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MSC8112 датащи(HTML) 30 Page - Freescale Semiconductor, Inc

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MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev. 0
Electrical Characteristics
Freescale Semiconductor
30
2.5.7
TDM Timing
Table 21. TDM Timing
No.
Characteristic
Expression
1.1 V Core
Units
Min
Max
300
TDMxRCLK/TDMxTCLK
TC1
16
—
ns
301
TDMxRCLK/TDMxTCLK high pulse width
(0.5
± 0.1) × TC
7
—
ns
302
TDMxRCLK/TDMxTCLK low pulse width
(0.5
± 0.1) × TC
7
—
ns
303
TDM receive all input set-up time
1.3
—
ns
304
TDM receive all input hold time
1.0
—
ns
305
TDMxTCLK high to TDMxTDAT/TDMxRCLK output active2,3
2.8
—
ns
306
TDMxTCLK high to TDMxTDAT/TDMxRCLK output
—
10.0
ns
307
All output hold time4
2.5
—
ns
308
TDMxTCLK high to TDmXTDAT/TDMxRCLK output high
impedance2,3
—
10.7
ns
309
TDMxTCLK high to TDMXTSYN output valid2
—9.7
ns
310
TDMxTSYN output hold time4
2.5
—
ns
Notes:
1.
Devices operating at 300 MHz are limited to a maximum TDMxRCLK/TDMxTCLK frequency of 50 MHz.
2.
Values are based on 20 pF capacitive load.
3.
When configured as an output, TDMxRCLK acts as a second data link. See the MSC8112 Reference Manual for details.
4.
Values are based on 10 pF capacitive load.
Figure 18. TDM Inputs Signals
Figure 19. TDM Output Signals
TDMxRCLK
TDMxRDAT
TDMxRSYN
300
301
302
303
303
304
304
TDMxTCLK
TDMxTDAT
TDMxTSYN
305
306
308
307
300
301
302
310
309
TDMxRCLK



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