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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MSC8112 датащи(PDF) 17 Page - Freescale Semiconductor, Inc |
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MSC8112 датащи(HTML) 17 Page - Freescale Semiconductor, Inc |
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17 / 44 page  Electrical Characteristics MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev. 0 Freescale Semiconductor 17 In all cases, the power-up sequence must follow the guidelines shown in Figure 8. The following rules apply: 1. During time interval A, VDDH should always be equal to or less than the VDD/VCCSYN voltage level. The duration of interval A should be kept below 10 ms. 2. The duration of timing interval B should be kept as small as possible and less than 10 ms. Figure 7. Start-Up Sequence: VDD Raised Before VDDH with CLKIN Started with VDDH Figure 8. Power-Up Sequence for VDDH and VDD/VCCSYN Time o.5 V 3.3 V 1.1 V VDDH Nominal PORESET/TRST asserted VDD Nominal CLKIN starts toggling VDD applied PORESET/TRST deasserted 1 VDDH applied VDDH = Nominal VDD = Nominal 3.3 V 1.2 V A B VDD/VCCSYN VDDH (IO) t (time) V |
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