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ST72334J2TA/XXX датащи(PDF) 127 Page - STMicroelectronics |
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ST72334J2TA/XXX датащи(HTML) 127 Page - STMicroelectronics |
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127 / 150 page ![]() ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto 127/150 EMC CHARACTERISTICS (Cont’d) 15.7.3 ESD Pin Protection Strategy To protect an integrated circuit against Electrostat- ic Discharge the stress must be controlled to pre- vent degradation or destruction of the circuit ele- ments. The stress generally affects the circuit ele- ments which are connected to the pads but can also affect the internal devices when the supply pads receive the stress. The elements to be pro- tected must not receive excessive current, voltage or heating within their structure. An ESD network combines the different input and output ESD protections. This network works, by al- lowing safe discharge paths for the pins subjected to ESD stress. Two critical ESD stress cases are presented in Figure 76 and Figure 77 for standard pins and in Figure 78 and Figure 79 for true open drain pins. Standard Pin Protection To protect the output structure the following ele- ments are added: – A diode to VDD (3a) and a diode from VSS (3b) – A protection device between VDD and VSS (4) To protect the input structure the following ele- ments are added: – A resistor in series with the pad (1) – A diode to VDD (2a) and a diode from VSS (2b) – A protection device between VDD and VSS (4) Figure 76. Positive Stress on a Standard Pad vs. VSS Figure 77. Negative Stress on a Standard Pad vs. VDD IN VDD VSS (1) (2a) (2b) (4) OUT VDD VSS (3a) (3b) Main path Path to avoid IN VDD VSS (1) (2a) (2b) (4) OUT VDD VSS (3a) (3b) Main path |
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