ST72334J2TASLASHXXX datasheet(90/150 Pages) STMICROELECTRONICS

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SERIAL COMMUNICATIONS INTERFACE (Cont’d)

13.5.5.3 Receiver

The SCI can receive data words of either 8 or 9

bits. When the M bit is set, word length is 9 bits

and the MSB is stored in the R8 bit in the CR1 reg-

ister.

Character reception

During a SCI reception, data shifts in least signifi-

cant bit first through the RDI pin. In this mode, DR

ternal bus and the received shift register (see Fig-

ure 47).

Procedure

– Select the M bit to define the word length.

– Select the desired baud rate using the BRR and

the ERPR registers.

– Set the RE bit, this enables the receiver which

begins searching for a start bit.

When a character is received:

– The RDRF bit is set. It indicates that the content

of the shift register is transferred to the RDR.

– An interrupt is generated if the RIE bit is set and

the I bit is cleared in the CCR register.

– The error flags can be set if a frame error, noise

or an overrun error has been detected during re-

ception.

Clearing the RDRF bit is performed by the following

software sequence done by:

1. An access to the SR register

2. A read to the DR register.

The RDRF bit must be cleared before the end of the

reception of the next character to avoid an overrun

error.

Break Character

When a break character is received, the SCI han-

dles it as a framing error.

Idle Character

When an idle frame is detected, there is the same

procedure as a data received character plus an in-

terrupt if the ILIE bit is set and the I bit is cleared in

the CCR register.

Overrun Error

An overrun error occurs when a character is re-

ceived when RDRF has not been reset. Data can

not be transferred from the shift register to the

TDR register as long as the RDRF bit is not

cleared.

When an overrun error occurs:

– The OR bit is set.

– The RDR content will not be lost.

– The shift register will be overwritten.

– An interrupt is generated if the RIE bit is set and

the I bit is cleared in the CCR register.

The OR bit is reset by an access to the SR register

followed by a DR register read operation.

Noise Error

Oversampling techniques are used for data recov-

ery by discriminating between valid incoming data

and noise.

When noise is detected in a frame:

– The NF is set at the rising edge of the RDRF bit.

– Data is transferred from the Shift register to the

DR register.

– No interrupt is generated. However this bit rises

at the same time as the RDRF bit which itself

generates an interrupt.

The NF bit is reset by a SR register read operation

followed by a DR register read operation.

Framing Error

A framing error is detected when:

– The stop bit is not recognized on reception at the

expected time, following either a desynchroniza-

tion or excessive noise.

– A break is received.

When the framing error is detected:

– the FE bit is set by hardware

– Data is transferred from the Shift register to the

DR register.

– No interrupt is generated. However this bit rises

at the same time as the RDRF bit which itself

generates an interrupt.

The FE bit is reset by a SR register read operation

followed by a DR register read operation.

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