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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST72334J2TA/XXX датащи(PDF) 50 Page - STMicroelectronics |
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ST72334J2TA/XXX датащи(HTML) 50 Page - STMicroelectronics |
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50 / 150 page  ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto 50/150 13 ON-CHIP PERIPHERALS 13.1 WATCHDOG TIMER (WDG) 13.1.1 Introduction The Watchdog timer is used to detect the occur- rence of a software fault, usually generated by ex- ternal interference or by unforeseen logical condi- tions, which causes the application program to abandon its normal sequence. The Watchdog cir- cuit generates an MCU reset on expiry of a pro- grammed time period, unless the program refresh- es the counter’s contents before the T6 bit be- comes cleared. 13.1.2 Main Features ■ Programmable timer (64 increments of 12288 CPU cycles) ■ Programmable reset ■ Reset (if watchdog activated) after a HALT instruction or when the T6 bit reaches zero ■ Hardware Watchdog selectable by option byte ■ Watchdog Reset indicated by status flag (in versions with Safe Reset option only) 13.1.3 Functional Description The counter value stored in the CR register (bits T[6:0]), is decremented every 12288 machine cy- cles, and the length of the timeout period can be programmed by the user in 64 increments. If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T[6:0]) rolls over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle pulling low the RESET pin for typical- ly 30µs. Figure 28. Watchdog Block Diagram RESET WDGA 7-BIT DOWNCOUNTER fCPU T6 T0 CLOCK DIVIDER WATCHDOG CONTROL REGISTER (CR) ÷12288 T1 T2 T3 T4 T5 |
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